
Alternative System Concepts Inc (AKA: ASC Inc) Profile last edited on: 10/26/2016
CAGE: 0LUH1
UEI:
Business Identifier: Electronic Design Automation: innovative EDA tools for high-level design flows to meet requirements for * Interoperability * Hardening/soft error recovery * Low power * Testability Is this YOUR Company?
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Location Information
Location: Single
Congr. District: 02
County: Rockingham
Congr. District: 02
County: Rockingham
Public Profile
Alternative System Concepts Inc. (ASC) performs funded basic research and advanced product development for electronic design automation. ASC creates and licenses innovative EDA tools for high-level design flows. SBIR funding has provided major support for the development of breakthrough methodologies that equip customers with innovative design tools, giving them a distinct competitive advantage for meeting tomorrow's challenging requirements for interoperability, testability, soft error recovery and lowest power. EDA tool licenses: HDL Translation - ASC's popular VHDL2verilog and verilog2vhdl Translators are now licensed and supported by SynaptiCAD (go to http://www.synapticad.com); VBIT® - IEEE Std 1149 JTAG RTL Insertion - Preliminary support for IEEE Std 1500 CTAG is also available; CoolChip - High-level power optimizing design flow using PACIFIC and macro block library elements such as ALF or popular design libraries; PACIFIC - ESL Power Optimizer automatically explores the design space for best architecture that meets timing constraint for dramatic reduction in switching and leakage power. Removes the guesswork from low power analysis and design; CORAL - Characterizes RTL macromodels for power for use in ESL flows. Examples of macro-block library components are adder, multiplier, mux, etc. CORAL supports IEEE Std. 1603 ALF and popular industry library formats; OpenALF is the open source ALF Compiler written in Perl. Technology module licenses: Save valuable project time by embedding proven software. Cross license one our reusable modules (C++, XML, and/or Python): * FRITS VHDL or Verilog parse tree * IEEE Std 1603 ALF Compiler and API * Behavioral fault modeling * Hardware/software co-design * Radiation hardening by design (also for soft errors) * VTMR soft error correction
Extent of SBIR involvement
Synopsis: Awardee Business Condition
Employee Range
5-9Revenue Range
.5M-1MVC funded?
NoPublic/Private
Privately HeldStock Info
----IP Holdings
N/AAwards Distribution by Agency
Most Recent SBIR Projects
Year | Phase | Agency | Total Amount | |
---|---|---|---|---|
2003 | 1 | MDA | $70,000 | |
Project Title: Rapid Radiation Failure Analysis of Digital Circuits Using a Computing Farm | ||||
2001 | 2 | MDA | $1,761,237 | |
Project Title: Rad Hard Very Deep Submicron Design by Concurrent Error Recovery | ||||
2000 | 2 | Army | $819,995 | |
Project Title: Low Power Behavioral Synthesis For Control-Flow Intensive HDL Designs | ||||
1997 | 2 | NSF | $474,995 | |
Project Title: Boundary Scan and Built-In Self Test (BIST) Insertion into VHDL Designs with Commercial Off-the-Shelf (COTS) Components or Embedded Cores | ||||
1996 | 2 | AF | $829,884 | |
Project Title: VHDL Behavioral Synthesis Tool for Low Power Based on FRITS |
Key People / Management
Carl A (Jake) Karrfalt -- President
Robert S MacDonald -- Controller
Sequei A Sokolov
Casper B Stoel
Alex N D Zamfirescu -- Vice President Engineering
Robert S MacDonald -- Controller
Sequei A Sokolov
Casper B Stoel
Alex N D Zamfirescu -- Vice President Engineering
Company News
There are no news available.