SBIR-STTR Award

Low power has been recently elevated to one of the most critical issues in VLSI circuit design, affecting packaging, cooling, and reliability characteristics. Although power optimization at behavior level was shown to have an order of magnitude higher impact than at logic or transistor level, no commercial tools presently exist for power optimization at high levels of design abstraction. ASC and Princeton University (Princeton) propose to develop a behavioral synthesis and power optimization tool for control-intensive HDL designs. The Phase I effort will integrate state-of-the-art methods of behavioral synthesis of control circuits with Princeton's unique power optimization technology through (1) implementation of synthesis and power optimization algorithms for control circuits, (2) evaluation of behavioral transformations for effective power reduction, (3) development of an approach to fast RT-level power and true delay estimation, and (4) implementation and evaluation of a prototype tool. The proposed R&D effort will leverage off ASC and Princeton's technology for power optimization in data-intensive designs being developed under an SBIR contract from the Air Force. In Phase II, the proposed new tool will be perfected and integrated with popular commercial design flows.

Potential Commercial Applications:
The ultimate commercial application of this effort will be a software product to be used for high-level design of integrated circuits where power is a critical specification. The tool will enable radical power reduction in control-intensive designs. Its impact on space electronics will be dramatic and will enable lighter payloads.

Alternative System Concepts (ASC) and Princeton University (Princeton) propose to complete research and development and start productization of an HDL-based behavioral synthesis tool for power optimization - PowerBuster TM-C. The tool will support trading off power, area, and speed requirements during design of complex microelectronic chips from behavioral specifications. New highly effective synthesis technology, developed and prototyped during Phase I, enables behavioral synthesis and power optimization of control-flow intensive designs. Power reduction up to 85% was demonstrated on selected test cases. This functionality is not presently available commercially, and represents advancement of state-of-the-art in Electronic Design Automation technology. In Phase II ASC will productize the Phase I technology, as well as develop and test new algorithms and techniques, such as memory power optimization, hierarchical synthesis of control-flow intensive designs, and power management during behavioral synthesis. A graphical user interface will simplify behavioral input capture. Effectiveness of the tool will be evaluated at ASC using public domain benchmarks, as well as, at the new JPL Collaborative Design Laboratory on real-world design cases. Industry interest is high as affirmed by several companies who supplied letters pledging IRAD support, early purchase of products and training. Overall cost sharing exceeds one million dollars.

Benefits:
The proposed low power design tool will have immediate benefit to the Army Land Warrior and the DARPA Small Unit Operations Situational Awareness System programs, as well as several commercial products, such as lap-top computers and wireless products. One major semiconductor manufacturer plans to phase in the ASC low power design technology for their early year 2000 production runs.

Keywords:
LOW POWER BEHAVIORAL HDL POWER OPTIMIZATION LAND WARRIOR BATTERY LIFE POWER SAVING ENERGY SAVIN