SBIR-STTR Award

VLSI systems implemented in VDSM technology are vulnerable to radiation effects such as neutron, total ionizing dose, transient dose, and Single Event Upsets (SEU). ASC proposes to develop an EDA tool for the reconfiguration and optimization of behavioral VHDL into RTL synthesizable code for radiation hardened designs. This will require an extension of the proven technology that was developed for reducing power in DSP in fixed architecture semiconductor circuits. Off-line testing and on-line fault-tolerance techniques will be applied to detect errors and correct them "on the fly." ASC will use XML information architecture and methods for these EDA tools. A comparative study of existing XML resources and methods will be conducted. The goal is to create and utilize spare capacity for error checking. The validation laboratory at Boeing will be used because this independent resource has the facilities and expertise to validate the functional performance of new Rad Hard designs that have been optimized by the new ASC Reconfiguration Tool.Anticipated Benefits/Commercial Applications: The ASC Reconfiguration Tool will equip designs for radiation tolerance by creating and utilizing spare capacity for error checking. Both military and commercial markets can benefit from radiation tolerance achieved through circuit design rather than expensive foundry qualification.

Mitigation of Single Event Upset (SEU) to electronic devices and components has traditionally been and expensive problem to overcome. Dramatic improvements in electronics technology have rendered many prior SEU solutions ineffective and have created the need for more advanced and innovative design tools. One of the more promising SEU solutions has been triple modular redundancy (TMR), where each processing and control circuit path is tripled and voted, such that when the outputs of the three circuit paths are not the same, assuming single failure, the odd circuit is disregarded. Through an algorithmic approach, the same results can be obtained with single circuits by reusing idle clock cycles. Such an approach is far more economical, and more reliable, became there is no need to triple the circuit. Except for a small increase in area and power, a radiation hardened circuit can be produced for the same cost, area and power as a non rad-hard commercial component. The feasibility of developing a tool named ART (Automatic Reconfiguration Tool) to create Virtual Redundancy in circuits was proven during Phase I, which included a demonstration at Space and Missile Defense Command in Huntsville, Alabama on September 12, 2000. Anticipated Benefits/Commercial Applications: Improve reliability and radiation tolerance of electronic devices efficiently through automated circuit reconfiguration in design phase. Specifically, the program will create a tool able to modify a completed design to add tolerance even to Single Event Upsets(SEU), the radiation effect which eludes most hardening techniques. The concept allows a completed design to be reconfigured with minimal added overhead to provide radiation tolerance and improved reliability through circuit design.

Keywords:
Electronic, tool, mitigation, SEU, design, radhard, redundancy, reliability