The proposal involves study of wafer to wafer, and device to wafer interconnect technologies that can provide > 1M interconnects per wafer (200mm). Silicon wafers with high density routing and high density -- 20 micron and 10 micron diameter-- TSVs (Through Silicon Vias), provide the starting substrate. Thermo-mechanical modeling studies will be done to assess the interconnect structure and interconnect material set. Based on the study and process integration analysis, a test vehicle will be designed. Short loop (no TSVs) and full loop (with TSVs) will be built. Wafer to wafer interconnection processes are evaluated first using short loop wafers followed by full loop wafers. Electrical testing along with X-ray and other monitoring techniques will be used to evaluate the wafer to wafer assemblies. Silicon to Silicon, Silicon to Glass wafer interconnects will be evaluated. Gross reality check reliability testing (100 cycles of thermal cycling) is planned to get a preliminary idea of the robustness of the interconnect. Additionally, we plan to evaluate alternate device material assemblies. After the results are obtained and analyzed, plans for follow up development and commercialization of the technology are proposed.
Benefit: Will provide a very high density interconnect technology that will help (1) improve device integration density, (2) improve performance by reducing parasitics,(3) provide design flexibility by allowing heterogeneus and homogeneous integration of devices, and (4) added potential to reduce overall cost per function in keeping up with trends of Moore's law. Developed technology will be applicable for both commodity and special purpose systems, especially ones where very high frequency performance is needed.
Keywords: 3D integration, 3D integration, 3D technology for wafers., High density stacking with TSV and TGV wafers/devices, Heterogeneous Device / Wafer Stacking, High Density Device to Device/Wafer Interconnect, Wafer to Wafer Interconnect
