Measurements of the hysteresis characteristics and switching kinetics will be made on three ferroelectric thin-film memory materials: lead germanate with 0 to 10% silicon (pb[5]ge[3-x]Si[x]o[ll]); bismoth titanate (bi[4]ti[3]0[12]); and potassium nitrate (kno[3]). Emphasis will be placed in determining the rate-limiting parameter for switching (e.g., sideways domain wall speed in the case of kno[3]), dependence of switching times upon film thickness, cell area, and external load. In kno(3) it is known that there is a minimum in the dependence of switching voltage upon thickness with a thickness window of 65 to 800 nm over which switching voltages lie below a 4.5v (the standard ttl/CMOS logic levels for silicon integrated circuits). This thickness dependence will be determined for pb(5)ge(3-x)si(x)o(ll) and bi(4)ti(3)0(12) in the present work. In the case of the lead Germans ate alloys, the addition of silicon is proposed to eliminate (or at least minimize) the problem of leakage current in the memory cells. Fatigue studied will be made with emphasis upon the theoretical model of srolovitz. Switching times demonstrated by the principal investigators of this proposal for kno(3) thin-film memories are already nearly within the limits requested in the program description: 1.6 to 1.8v threshold and a 20 ns switching time at 6 to 9v.
