Crypto capabilities are widely adopted by government and commercial electronic devices to protect data, communication, and other essential operations. Although considered more secure compared to their software counterparts, hardware implementations of crypto algorithms are vulnerable to more sophisticated attacks such as side-channel attacks and reverse engineering. It is imperative to equip such hardware crypto modules with higher level of security in mitigating such attacks. The goal of this project is to develop a polymorphic crypto module, e.g., AES, which is capable of using two sets of keys based on the supply voltage provided by the system. For example, in GF12nm process, if 800mV is provided, the AES module will use key#1 for encryption/decryption; if 450mV is provided, the module will use key#2. When incorporated into an ASIC/SoC, since this supply voltage is internal, attackers do not have access to this information, making their attacks to the crypto module extremely difficult. This module can be incorporated into any ASIC/SoC, e.g., microprocessor, microcontroller, machine learning accelerator, etc., which requires crypto capabilities with high security. Polymorphic circuits refer to special circuit designs where a fixed CMOS digital circuit is capable of carrying out two or more distinct functions based on changes in the supply voltage. Since these functions are embedded into logic gates, the area is much smaller compared to if all functions are standalone due to the sharing of transistors inside each gate. Unfortunately, the clocked, synchronous polymorphic circuits are impractical to design due to their strict timing requirements. Timing closure is hard enough for modern digital ASICs possessing only one function. Having multiple functions at different supply voltages is a much worse scenario for timing analysis. A timing-robust design paradigm is needed to make polymorphic circuits practical.
