SBIR-STTR Award

This Small Business Innovative Research (SBIR) Phase I project is to meet the increasing need for commercial-off-the-shelf (COTS) components in the ever shrinking time to market in the electronics industry. COTS components are readily available, less expensive, and increase efficiency of the design process, but negatively impact testability. It is proposed to develop a methodology for enhancing testability of boards and systems implemented using COTS devices, and to provide the supporting tools. The methodology will improve controllability and observabilitv in such board testing through (1) implementation of board-level JTAG boundary scan, (2) borrowing boundary scan included on some chips to test surrounding COTS components without boundary scan, and (3) integrating other test and diagnostic techniques such as board-level built-in self test (BIST) and IDDQ test using the 1149.1 standard boundary scan serial interface. Industry standards (VHDL and Boundary Scan) support interoperabilitv with major EDA frameworks. During Phase I, a prototype tool set will be developed for higher level (board, Multi-Chip Module, etc.) boundary scan and BIST insertion into VHDL designs. In Phase II, tool set features and capabilities will be expanded, and product commercialization will begin. The proposed test insertion methodology provides a solution to pressing problems faced by designers whose design requirements include high testability and use of untestable COTS components. The new tool set will lower cost and save time in the design phase through use of commercial parts without the attendant compromises in testability.

This Small Business Innovation Research Phase 11 project provides a solution to deal with the negative impact that commercial off-the-shelf (COTS) components have on testability. The ever shrinking time-to-market, in the electronics industry, has created an increasing need for COTS components to slash development time. At the chip level, where Intellectual Property (IP) cores are being used, the main problem is controllability of the primary inputs and observability of the primary outputs of the embedded cores. ASC has developed a solution based on the boundary scan standard being applied to all cores. To avoid high circuitry overhead and long test times, ASC developed an optimization methodology during Phase I, which provides: Direct access to each embedded core, short test times, low hardware overhead, and flexibility in test configuration. During Phase II, ASC will enhance its existing VBIT(R) tool to allow designers to automatically insert optimized boundary scan in their chip designs with embedded cores. This new VBIT-MC (Multi-Core) tool will be integrated into existing EDA design flows, be capable of using existing test data, and have a graphical front-end. With a rapidly growing market for test tools and without competitors on the horizon, the commercial prospects for VBIT-MC are excellent.