SBIR-STTR Award

High Fidelity Analog Integration Techniques for High Temperature Applications
Award last edited on: 11/13/2024

Sponsored Program
SBIR
Awarding Agency
DOD : DARPA
Total Award Amount
$1,492,066
Award Phase
2
Solicitation Topic Code
NASA S4.04
Principal Investigator
Nicholas Chiolino

Company Information

Ozark Integrated Circuits Inc (AKA: Ozark IC )

700 West Research Center Boulevard
Fayetteville, AR 72701
   (479) 409-5201
   admin@ozarkic.com,info@ozarkic.com
   www.ozarkic.com
Location: Single
Congr. District: 03
County: Washingto

Phase I

Contract Number: 2022
Start Date: ----    Completed: 6/2/2022
Phase I year
2022
Phase I Amount
$1
Direct to Phase II

Phase II

Contract Number: N/A
Start Date: 7/1/2024    Completed: 6/2/2022
Phase II year
2022
(last award dollars: 1731503720)
Phase II Amount
$1,492,065

The battlefield of the future and today, is based on data; and the ability to act upon this data. Data provides the foundation of everything from intelligence, situational awareness, and force readiness. Acquiring data in extreme environments requires analog and mixed signal electronics that don’t need thermal management. Integrated circuits (ICs) made with silicon carbide (SiC) semiconductor technology at research laboratories, such as NASA ‘s JFET-R, has been shown to work reliably for 100s to 1000s of hours at 500°C. The next urgent step is to migrate the SiC process from R&D availability to regular quarterly production. Migration of this technology into a commercial-scale capable fab is the next logical step. General Electric Research Center (GERC) stands ready to work with Ozark IC to migrate the essential metalization steps (“Back End of Line”) to support greater JFET-based silicon carbide production. Analog and mixed-signal data acquisition systems also require precision passive elements, which are scarce if there is no thermal management. This second part of this project will develop additively manufactured (AM) passive structures designed to heterogeneously integrate with the ICs from the migrated JFET-R process. These AM passives will be printed and characterized over the full temperature range using passive test structures for schematic capture and simulation via thermally hardened SPICE models. This work will culminate in the design, fabrication, and packaging of an analog system for demonstration at high temperature. This system will include an analog JFET-R chip heterogeneously integrated with AM passives fabricated to match a schematic design of the complete system.