Commercial FPGA programming software tools use logic synthesis tools to route the connections between logic gates, look-up tables, and memory units. Current commercial tools, however, are optimized to maximize operation speed and minimize area and memory utilization. This proposal addresses the needs of the Department of Defense for a solution that provides a means of reducing FPGA power consumption for any specific target architecture. We proposed in this Phase I research to develop the LPS (Low-Power Synthesis) tool, a stand-alone software tool plugin for commercial synthesis tools that will optimize RTL designs for low-power. The LPS tool will take in an input RTL design and a set of design rules for the target FPGA architecture, perform a comprehensive set of low-power optimizations, and then generate an output RTL design for the backend logic synthesis tool. We will test the power optimizations and the LPS tool on a set of large multi-media benchmarks. Our proposed work will address DODâs requirements for a low-power synthesis tool by providing a generic entry point for virtually all commercial logic synthesis tools, providing a low-cost solution for low-power FPGA design, and providing an automated framework that will reduce low-power design times from months to hours.
Keywords: Fpga, Low Power, Design Rules, Logic Synthesis, Macro-Model, High-Level Synthesis, Rtl
