News Article

SEE Mitigation Technique for Self-Timed Circuits and Rad-Hard, Self-Timed Configurable Memory
Date: Dec 01, 2014
Source: TechBriefs ( click here to go to the source)

Featured firm in this article: GoofyFoot Labs LLC of Plano, TX



The new block RAM is faster and consumes less power than conventional block RAMs, while providing unparalleled levels of radiation resilience.

To enable NASA's next-generation missions, there is a critical need for a reconfigurable field programmable gate array (FPGA) that can withstand the wide temperature ranges and radiation of the space environment while consuming minimal power without compromising on performance. To address this need, GoofyFoot Labs developed the E2-AMP FPGA, a radiation-hardened, high-performance, low-power FPGA capable of operating reliably over wide temperature ranges and rapid thermal changes.

Triple modular redundancy (TMR) is a commonly used approach to mitigate the effects of single event transients (SETs). Because all circuits are triplicated, full TMR can require up to six times the area of the original circuit. TMR circuits are only immune to errors that affect one redundancy. If multiple redundancies are affected, functional failures can result. Furthermore, time redundancy can be applied at the software level to achieve SET tolerance; however, this approach incurs a significant speed penalty of as much as 354%. The SET-resilient logic style employed in the E2-AMP renders the FPGA immune to multiple SETs without incurring the significant penalties associated with conventional hardening techniques such as TMR and EDAC (error detection and correction). The 150-nm E2-AMP FPGA achieves 765-MHz peak performance at room temperature while consuming 5.5x less power than commercial 40-nm FPGAs implementing TMR and EDAC for hardening.

Because the E2-AMP FPGA targets extreme environments, all components must be capable of reliable operation in an extreme environment, including the memories. Achieving this goal using traditional memories puts significant burden on the FPGA designer to ensure that their applications work over the entire range of operating conditions. In addition, conventional designs place the burden of radiation hardening on the FPGA designer. The designer must implement EDAC to account for radiation-induced upsets. Furthermore, it is desirable for the block RAM to match the maximum operating speed of the FPGA logic fabric. Conventional block RAM designs at the 150-nm technology node of the E2-AMP FPGA do not operate sufficiently fast. GoofyFoot Labs developed a rad-hard, self-timed, configurable memory. This configurable memory, known as the block RAM (random access memory), serves as fast-on chip storage for FPGA applications that require memory.

The novel and unique features of the E2-AMP block RAM include the capability to operate over extreme temperature changes and ranges, and built-in radiation hardening at all levels, including a rad-hard SRAM cell, rad-hard memory support logic, EDAC capabilities, and layout techniques to further bolster radiation resilience. In addition, the E2-AMP block RAM is faster and consumes less power than conventional block RAMs, even while providing unparalleled levels of radiation resilience.

This work was done by Nisha Checka and Christopher Shirk of GoofyFoot Labs for Marshall Space Flight Center. For more information, contact Ronald C. Darty, Licensing Executive in the MSFC Technology Transfer Office, at Ronald.C.Darty@nasa.gov. Refer to MFS-33142-1/3-1.