Date: May 15, 2013 Source: (
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NanoWatt Design, Inc. has been awarded a $150,000 Small Business Innovation Research Phase I grant from the National Science Foundation. The grant will support the demonstration of Sleep Convention Logic™ (SCL), a new asynchronous circuit architecture, applied to an advanced multi-core microprocessor.
SCL has the potential to change the way that chips used in cell phones, laptops, tablets, and even servers are designed. For the project, the company is teaming with a $5B defense-aerospace customer that is developing an advanced parallel processor. The customer will provide circuit information to NanoWatt Design. NanoWatt Design will apply its proprietary software SCLCompiler™ to convert the existing processor design to the new technology. The circuit will then be optimized for low power. At project conclusion, NanoWatt Design will have side-by-side comparisons showing that the SCL architecture delivers lower power consumption, while meeting requirements for speed.
With mobile electronic devices connected to the internet, users constantly demand increased functionality and long battery life. Yet, increased functionality requires additional power. Power consumption has now replaced operating speed as the most crucial concern for designers. Particular importance is attached to standby leakage power, since users may interact intensively with their device for a few hours, set it aside for the rest of the day, and then expect the device to respond immediately when they pick it up. SCL meets these requirements by automatically sleeping any circuit when not in use, and waking with no delay.
"Sleep Convention Logic™ is an exciting innovation in digital circuit design," said Ronald B. Foster, Chief Executive Officer. "By supplying power only as needed, SCL addresses the growing demand for smarter, more complex digital devices such as GPS, smart phones, and even medical implants. Our technology is a compelling option for an almost unlimited range of digital applications."
NanoWatt Design, Inc. is commercializing ultra-low power Sleep Convention Logic™ circuit architecture. The company's patent-pending, asynchronous, Sleep Convention Logic™ (SCL) architecture promises dramatic reduction in power consumption of digital circuitry, while meeting requirements for speed. SCL technology is delay insensitive, making it very robust to variation. Additionally, NanoWatt Design's SCLCompiler™ software works seamlessly with industry standard design tools used in creating digital logic circuits. NanoWatt Design™ is a VIC Technology Venture Development™ portfolio company.
