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Tera Systems Inc
Profile last edited on: 4/6/06      CAGE:       UEI:

Business Identifier: front-end design planning technologies for use by designers of complex System-on-Chip (SoC) semiconductors.
Year Founded
1995
First Award
1997
Latest Award
1998
Program Status
Inactive
Popularity Index

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  Explanation Edit

Location Information

1741 Technology Drive Suite 300
San Jose, CA 95110
   (408) 790-2000
   N/A
   www.terasystems.com
Location: Multiple
Congr. District: 19
County: Santa Clara

Public Profile

Tera Systems develops front-end electronic design automation systems to estimate, optimize, and analyze the performance and density of systems-on-a-chip (SoCs) at the earliest stage possible in the chip design cycle. This dramatically improves designer productivity and accelerates back-end design convergence

Extent of SBIR involvement

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Phase I Awards
1
Phase II Awards
1
Conversion Rate
100.00%
Phase I Dollars
$99,703
Phase II Dollars
$729,505
Total Awarded
$829,208

Synopsis: Awardee Business Condition

Employee Range
25-49
Revenue Range
2.5M-5M
VC funded?
Yes
Public/Private
Privately Held
Stock Info
----
IP Holdings
5-9

Awards Distribution by Agency

Most Recent SBIR Projects
Year Phase Agency Total Amount
1998 2 AF $829,208
Project Title: A System for Register Transfer Level (RTL) Full-Chip Area, Speed, and Power Optimization

Key People / Management

  Motti Beck -- CEO

  Tommy Eng

Company News

There are no news available.