SBIR-STTR Award

Detecting changes in two-dimensional scenery requires three essential components: detection/recognition of object, computation of relative motion, and fast, compact processors to carry out the required numerical calculations. Traditionally, most emphasis is placed on the first two software components. A problem is that processing large 2-D arrays is a complex task reireing board level hardware. An attractive alternative approach to simply considering improved software, is to reconsider the hardware in conjunction with software algorithms. We have recently conceived of a novel spectral processor based upon reduced bit depth logic. Originally developed as a means for very rapid calculations of frequency (Doppler) spectra for laser radar applications, it appears that the same type of hardware processor can be applied to image correlation, and hence detection of motion within images. We propose to carry out further analysis of this processor in Phase I, with particular emphasis on extending correlation calculations to two dimensions. we also plan to build a scaled-down 1-D processor in Phase I, in order to demonstrate the viability of carrying out full-scale development in Phase II.

Keywords:
Image Processing Correlations Spread Spectrum Spectral Processing

In Phase I we have demonstrated the feasibility of fabricating single chip devices capable of calculating correlations with extremely high efficiency. The implemented algorithm is entirely linear, which enables simple scaling to very high speed (potentially >1 GHz clock speeds ) and scalability to data sets in excess of 1k points. In Phase I we have designed and simulated a 16 channel device, which will be implemented in hardware prior to the end of Phase I. Part of the interest in the devices is the capability to extract spectral information in a manner similar to an FFT, but with 100% use of input data (no bottlenecking and essentially zero latency. Further advantages include continuous update of correlation information on a single clock-cycle basis. In Phase II we propose to devleop full-size chips capable of processing at least 512 channels (1024 set as a goal) in a field-programmable gate array (FPGA) or ASIC capable of operating at a clock frequency of at least 200 MHz.

Keywords:
Dft Fft Correlator Signal Processing Spectral Processing Fast Fourier Transform