SBIR-STTR Award

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project is to accelerate the adoption of AI features in Internet of Things and mobile devices. The proposed multi-bit non-volatile memory (NVM) based Deep Neural Networks (DNN) IP is based on the standard CMOS logic processes. Existing solution for the DNN hardware typically requires off-chip access to retrieve neural network parameters from external memories, incurring additional communication latency and power consumption. Additionally, when critical neural network parameters are transmitted off-chip, security or privacy concern may arise, which is unacceptable especially for the applications such as personalized AI devices. Alternative approach integrating the DNN engine in a special NVM process requires as much as 10 additional masks beyond the conventional logic CMOS process which is not cost-effective for medium density DNN engine in cost-sensitive edge devices. With this proposed IP, any existing or new system on chip requiring persistent AI functionality can be built quickly and cost effectively.This Small Business Innovation Research (SBIR) Phase I project seeks to develop a cost-effective non-volatile neural network accelerator IP for edge devices. To solve the security, latency, power consumption, and cost issues associated with the traditional approaches, a single-poly based low cost, non-volatile, multi-bit eFlash cell is proposed. Multi-bit cell operation however presents significant challenges due to inherent reduction in signal-to-noise ratio. Key technical hurdles include solving disturbances of unselected cells, improving sensing margin, and overcoming reliability issues associated with high voltage operation in readout circuits as well as developing robust neural network cell arrays. To address these challenges, several new ideas related to multi-bit cell, high-voltage circuits, and cell programming methods have been proposed. Once verified successfully in this project, the multi-bit cell IP can then be integrated as logic compatible non-volatile memory to store neural network parameters on-chip, or as logic compatible non-volatile neural network IP to execute entire neural network operation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to enable energy efficient smart internet of things (IoT) devices capable of running a neural network locally. The proposed energy-efficient neural network accelerator solution uses circuit architecture that allows for chips with a small area, a key enabler for cost-effective adoption and inclusion in space-constrained systems such as mobile devices. The solution is energy-efficient compared to the existing digital logic-based accelerator solutions, which will enable edge implementation for systems with power constraints. The manufacturing process is fully scalable in advanced standard logic processes at almost all manufacturing foundries, thus allowing for widespread adoption of the architecture. The outcome of this project will be an energy-efficient system on a chip (SoC) solution that offers artificial intelligence integration in smart IoT devices without cloud access, while enabling security and privacy enhancements. This Small Business Innovation Research (SBIR) Phase II project seeks to further develop an energy efficient analog circuit topology and variation tolerable system solution. To enable analog compute-in-memory architecture based neural network accelerator solution in an advanced semiconductor process technology, significant design challenges need to be solved with reduced supply voltage and noise margin. Along with the newly proposed area efficient and performance efficient analog compute-in-memory architecture solution, the logic compatible non-volatile neural network accelerator intellectual property core will be designed, fabricated, and validated in the advanced process technology through the project. Once verified successfully from the fabricated silicon in this project, the proposed neural network IP will be ready to be integrated as a key building block of future artificial intelligence systems on a chip and enable energy-efficient smart edge IoT devices.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.