SBIR-STTR Award

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase I project will be to enable various low latency video applications that are not possible today. One of the most interesting is in the area of cloud computing, in which a server in a data center somewhere on the Internet runs a client's application remotely, and delivers the frame-by-frame video to the client's viewer. This allows for a very cheap client device, consisting of just a video decoder and an input such as a mouse pad, while graphic or compute intensive tasks run on powerful servers in the cloud that can be leased to the client on an as-needed basis. This server-client model could also be used internally at a company or school, greatly simplifying IT requirements. And for high security applications there is also an advantage, as all data is stored remotely. There is nothing local on the user's device to be compromised. Cloud computing services such as these are already coming on line, but the range of applications they can run is limited by the lack of good low latency video encoding. Solving this problem opens up a whole new paradigm of how people purchase, maintain and use personal computers and software.

This Small Business Innovation Research (SBIR) Phase I project investigates techniques for real-time ultra low latency video compression. The goal of the research is to enable the encoding and transmission of video over a communications medium such as the Internet, cell phone network, satellite network, etc. such that the video may be viewed at the receiving end with no more than 1 frame of latency from when it was encoded at the source. The best and newest industry-standard video compression specification, called H.265, will be used as a framework such that the resulting compressed video can be readily decoded by widely available software or hardware. Framework tools and techniques to monitor and adjust the bit rate of the compressed video will be developed and tested to achieve the low latency goals while maintaining high visual quality of the compressed video. The result of this research will be a set of algorithms that can be used in the design of an H.265 video encoder that will achieve the low latency goal, as well as a characterization of the limitations of these algorithms such that their applicability to various real-world opportunities can be assessed.

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project is to promote and improve the use of high quality video in products that the general public works with every day. From high resolution auto dashboard cameras, to low latency video streams from flying drones, to wireless laptop docking stations, to higher quality coverage of news and sporting events, to better and faster delivery of video over the Internet, every application requires the high quality, low latency, flexible, power efficient video encoders that will be developed in this project. The uses of video are increasing every day. Video instruction manuals are replacing printed instruction manuals. Video is replacing still images in on-line advertising, social media and billboards. It is predicted that over 90% of all Internet traffic will be video data in the next few years. Enabling all these applications requires the latest technology in video compression such as the techniques developed in this project.This Small Business Innovation Research (SBIR) Phase II project tackles the problem of creating a real time video encoder, using the latest H.265 compression technology, running in hardware on an FPGA (Field Programmable Gate Array). An FPGA is a type of chip on which the logic is configurable - it can be programmed to implement any function. It represents a mid-point between a dedicated integrated circuit, which is very expensive to develop, and can never be changed or enhanced once it is fabricated, and a pure software solution which is very flexible but requires bulky and power hungry equipment (i.e. computers) as an underlying platform. The research conducted under this grant will devise, test, and implement algorithms that are amenable to realization on an FPGA, that operate in real time, and that yield a high quality result in terms of the visual quality of the compressed video with respect to the number of bits used. The goal, at the conclusion of this research, is the demonstration of a functional HEVC/H.265 encoder running on an FPGA which has cost, flexibility, power and performance advantages over other encoders.