SBIR-STTR Award

This Small Business Innovation Research (SBIR) Phase I project targets development of a radiation-hard IC design technology at the transistor level. This will enable the design and production of radiation-hard devices using standard CMOS processing, with an order of magnitude improvement in radiation tolerance compared to standard transistor designs. The proposed approach uses innovations in IC transistor design and layout methods which, while maintaining the performance of standard CMOS integrated circuits, greatly increase their radiation tolerance. The ability to use existing advanced CMOS IC designs and processes will enable better performance from the electronics and extend electronics life in high-radiation applications. An early application of this technology will be the signal processing electronics used in CT scanners, with an objective of reducing radiation exposure experienced by patients and medical personnel during CT scans. This project will enable production of sensor signal processors that could be positioned as close to the X-ray detectors as desired, directly in the X-ray beam path, and ultimately integrated with detectors. The objective of this Phase I project is to provide proof-of-concept of methods to greatly improve the radiation tolerance of integrated circuits in designed in standard CMOS, for use in CT-scanner electronics and other high-radiation applications. The broader impact/commercial potential of this project will be to provide CT-scan equipment manufacturers the capability of building CT-scanners offering significantly reduced exposure by enabling the placement of detector electronics in direct proximity to X-ray detector rows. The key to the ability to address the market for CT scan equipment electronics with this improved radiation exposure technique is the ability to design radiation-hard ICs in standard semiconductor processes. This project targets the improvement of IC radiation hardness by the use of design techniques within existing commercial processes, rather than by developing costly new processes. Dose reductions in medical and dental X-rays, body scanners used for national security, and related systems would reduce societal health risks and the incidence of cancer. The project will enhance scientific and technological understanding of radiation effects on CMOS integrated circuits, as well as providing methods to improve their radiation tolerance. Radiation-hard electronics could be more easily developed for a wide range of applications where reliability is essential.

The broader impact/commercial potential of this Small Business Innovation Research (SBIR) Phase II project will be to develop and commercialize radiation-tolerant integrated circuit (IC) technology for producing radiation-tolerant/hardened (rad-hard) ICs capable of being manufactured using leading-edge commercial IC processing instead of expensive specialized processes which use older, less efficient lithography nodes. The direct customers for the technology, to be delivered in the form of Electronic Design Automation (EDA) tools and support services, will be semiconductor integrated device manufacturers and semiconductor foundries. In the CT scanner industry, improved radiation-tolerance of the electronics will allow key components to be placed directly in the X-ray path, improving signal quality, and resulting in better images at reduced X-ray dose levels to patients. Reducing X-ray exposure from CT scans is a medical priority, as it has been estimated that 0.4% of current cancer incidents result from high X-ray doses from CT scans. Application of the patent-pending technology in radiation-hard ICs for a wide range of other commercial radiation-environment markets will follow, including commercial satellites, nuclear-power electronics, nondestructive testing, and medical electronics sterilization. This Small Business Innovation Research (SBIR) Phase II project will provide integrated circuit (IC) designers access to leading-edge IC technology and advanced lithography nodes in developing ICs for radiation-tolerant applications, and is based on patent-pending transistor-level design and layout innovations and their implementation in EDA tools. In Phase I, proof-of-concept was established; transistor structures evaluated for X-ray and gamma radiation tolerance improved by a factor of 7 for 1.8V transistors, and by well over a factor of 10 for 5V transistors, with the use of the technology. The research objective of Phase II is to provide ready access to the benefits of the technology to IC designers by incorporating the methodologies for transistor-level design and layout improvements into industry-standard EDA tools. A number of technical challenges will be addressed in Phase II, including optimizing the tools for producing area-efficient and cost-efficient transistor layouts, and assuring seamless integration with existing design flows. A beta version of an EDA tool kit will be developed in Phase II; the anticipated result will be a tool that can be used by initial customers in producing rad-hard ICs used in CT scan electronics and other applications.