This Small Business Innovation Research (SBIR) Phase 1 project will use normally-available data produced by failing integrated circuits (ICs) to evaluate the capability of design-for-manufacturability (DFM) rules and guidelines to ensure reliable, working ICs. All ICs employ DFM rules and guidelines that are constraints that prevent or limit the use of certain physical structures within the IC. Such structures are constrained since they are difficult to manufacture implying they have a less-than-acceptable likelihood for causing chip failure. Thus DFM is meant to ensure ICs yield at acceptable levels. Deployment of DFM does have a cost however since its application requires the use of complex design tools that typically require weeks of compute time to check for design compliance. Moreover, performance degradation results when the IC is modified to satisfy DFM constraints. While the costs of DFM are clear, there is however no direct way of measuring DFM effectiveness. In other words, how well a specific rule or guideline actually ensures yield is an open question. This SBIR project will develop and implement software that analyzes the design data and tester data from failing ICs to directly measure the effectiveness DFM rules/guidelines. The broader impact/commercial potential of this project is that it will enable chip designers and manufacturers to employ only those DFM rules/guidelines that are actually effective. This means that chip yield will improve since the overall design will be more manufacturable, chip quality will improve since systematic failures that are more likely to escape detection will be reduced, chip design cost will decrease since the time needed to deploy DFM will be reduced since only the effective rules will be used, and chip performance will improve since the design will be altered less since only the most effective rules will be used
