SBIR-STTR Award

This Small Business Innovation Research Phase I research project is focused on improving the yield and quality of integrated circuits (ICs) thru information extraction from test measurement data. Yielding reliable, working integrated circuits (ICs) is becoming significantly more difficult as fabrication technology moves towards structures with even smaller and smaller dimensions. As a result, the traditional testing task of determining if every manufactured IC is correct and reliable is also growing in importance. But beyond its traditional sort function, test has to become a major feedback mechanism for improving yield and quality. Standard practices involving in-line inspection, wafer-level test structures, and physical failure analysis are losing effectiveness and must be augmented with new methodologies that mine IC test measurement data for critical information that enable improvements in both yield and quality. This proposal plans to maximize knowledge extraction from IC test data by extending the patent-pending, state-of-the-art test and diagnosis methodologies to cope with more complex failure mechanisms and the increasing complexity of modern ICs. The broad impact of the research proposed here centers on continuing the advancement of the $250B U.S. semiconductor industry. There is significant commercial opportunity in supplying test data analysis on a per-design basis to both Integrated Device Manufacturers and fabless design houses that enables them to improve yield and quality through feedback from IC testing. Manufacturers will use this information to fine-tune their fabrication processes to maximize yield and performance, and optimize their test methodologies to ensure quality meets customer demands

This Small Business Innovation Research (SBIR) Phase II project develops an automated, software-based analysis methodology that enables yield and quality improvement of integrated circuits (ICs) through information extraction from test measurement data. Deriving actionable information from test data is a challenging task due to lack of software that automatically correlates test measurement data obtained from failing ICs and their physical IC-design description (i.e., the layout). Maximizing knowledge extraction is accomplished by a new software-based diagnosis technique that uses in conjunction the logical and layout descriptions, in addition to the measured test data, to identify at the nanometer scale, the precise location and type of defects within non-working ICs. The project also develops software-based statistical methods that find commonalities among the defects characterized within failing ICs. The combination of improved diagnosis and commonality analyses means that the root-causes for failure can be quickly found and passed on to designers, process engineers, and test engineers to guide remedy selection and deployment.The broader impact/commercial potential of this project centers on continuing the advancement of the US semiconductor industry which is vital to both Homeland Security and the general advancement of society as a whole. There is significant commercial opportunity in supplying test data analysis on a per-design basis to Integrated Circuit (IC) producers that enables rapid improvement in yield and quality through feedback from manufacturing testing. The potential impact is tremendous since specific, pertinent information is fed back to both designers and manufacturers about how and why ICs fail. Chip designers will use this information to improve design rules for producing high-yielding and ultra-reliable ICs. Chip manufacturers will use this information to fine-tune their fabrication processes to maximize yield and performance, and optimize their test methodologies to ensure quality meets customer demands. It is also anticipated that this technology will also spur further research and broaden the scope of research in universities.