SBIR-STTR Award

A Direct-Write Probe Card Fabrication Process
Award last edited on: 12/23/2003

Sponsored Program
SBIR
Awarding Agency
NSF
Total Award Amount
$99,553
Award Phase
1
Solicitation Topic Code
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Principal Investigator
Richard J Casler

Company Information

Picosys Inc (AKA: Invenios Inc)

320 North Nopal Street
Santa Barbara, CA 93103
   (805) 962-3333
   N/A
   www.invenios.com
Location: Single
Congr. District: 24
County: Santa Barbara

Phase I

Contract Number: ----------
Start Date: ----    Completed: ----
Phase I year
2003
Phase I Amount
$99,553
This Small Business Innovation Research (SBIR) Phase I Project addresses low cost fabrication of probe cards for use in testing advanced circuit technologies. Currently, high-density probe card assemblies employ more than 1500 test points to provide the increased test coverage necessary for System-on-a-Chip and high pin count devices. At $50/test point, such assemblies often sell for over $75,000 and they wear out in only 1 million wafer touchdowns. These assemblies often require integration of multiple components-sometimes thousands-and require many hours of labor to assemble. This project would promote nanoparticle-based meso-film; laser patterned optical-quality glass ceramics; and inkjet printing processes that will reduce the probe card manufacturing cost, increase test point density, increase contact life, and reduce assembly labor. The Phase I project will be a collaboration of several companies bringing together expertise in 3D laser patterning; material and process development; and nanoparticle manufacturing in a unique and powerful way to tackle an important industry challenge. The commercial application of this project is in testing of advanced electronic circuits in such uses as processes for the manufacture, deposition and functionalization of nanoparticle-based coatings with low sintering temperatures; feature resolution of laser patterned substrates for 3D micromachining applications including MEMS, MOEMS, microreplication, and grating manufacture; test integration-optical, mechanical, and electrical wafer testing being combined in a monolithic substrate; faster product development cycle times and production ramps for advanced processor and microsystem designs; and design of test fixtures for the new wave of electronic products built using direct-write deposition of passive and active electronic structures onto non-silicon substrates

Phase II

Contract Number: ----------
Start Date: ----    Completed: ----
Phase II year
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Phase II Amount
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