This Small Business Innovation Research (SBIR) Phase I project investigates a Computer Aided Failure Analysis System (CAFES) for rapid diagnosis of yield loss for digital VLSI circuits. Such a system is needed to accelerate the yield learning for semiconductor fabrication facilities. Traditional approaches to yield learning involve diagnosing the faulty component, and subsequently determining the underlying contaminant through costly and time-consuming physical failure analysis techniques. Turnaround time to obtain a statistically meaningful sample of contaminants slows yield learning. The rapid failure analysis research methodology of this Phase I combines traditional defect localization with automatic defect classification techniques. These automatic techniques directly relate circuit malfunctions to possible contaminants, thereby alleviating the requirement for physical failure analysis methods. This is accomplished through off-line characterization of the faulty device and augmented cell library information which catalogs the possible faulty behaviors of the device. The research will study required algorithms and write a prototype code to establish the accuracy and resolution which this scheme can attain. Reducing the time required to achieve profitable yields will increase profitability. The cost benefits of CAFES are important in the face of mounting costs of semiconductor fabrication facilities. Rapid yield learning is one of the important options for enhancement of competitive advantage in the semiconductor manufacturering industry.
