SBIR-STTR Award

Advanced Hardware Scheduler for Parallel Processing
Award last edited on: 11/22/02

Sponsored Program
SBIR
Awarding Agency
NSF
Total Award Amount
$74,395
Award Phase
1
Solicitation Topic Code
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Principal Investigator
Larry E Wilbur

Company Information

Belobox Systems Inc

18 Technology Drive Suite 130
Irvine, CA 92618
   (949) 727-4115
   belobox@belobox.com
   www.belobox.com
Location: Single
Congr. District: 47
County: Orange

Phase I

Contract Number: 9560140
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1995
Phase I Amount
$74,395
This Small Business Innovation Research Phase I project will advance the implementation of Symmetric MultiProcessing (SMP) computers by providing a commercially available hardware scheduler to replace the inadequate scheduling software used by all operating systems. Hardware scheduling is a critical enabling technology in the evolution of sophisticated parallel processing computing systems that simplifies scheduling of complex multithreaded applications, permits inter-SMP computer scheduling, eliminates the extremely complex scheduling software, and ensures that all processors are always executing applications code in place of scheduling. The objective of the research is to make a commercially available product that will benefit a wide range of operating systems and hardware platforms by specifying a simplified operating system interface to support any processor and validating that a full implementation of a sub-microsecond hardware scheduler is feasible using commercially available, large programmable hardware components. The research will include preparation of a software requirements document to permit any operating system to be easily interfaced to the hardware scheduler, preparation of a hardware requirements document for the hardware scheduler's behavior, investigation of commercially available, large programmable hardware components with the capabilities of meeting the requirements of the hardware scheduler, selection of several components, and verification that the required logic can fit in the components and obtain sub-microsecond hardware scheduling. At the end of the initial effort it is expected that all objectives will have been met permitting the building of a cost-effective, prototype hardware scheduler suitable for any processor running any operating system on any system bus. This prototype could then be put into production quickly and cost effectively. The hardware scheduler could become a part of every computer system, including single processor systems, because they would also benefit from elimination of software scheduling code. Therefore, any operating system would be capable of running SMP and inter-SMP scheduling without writing and maintaining the extremely complex scheduling software required for SMP scheduling. In addition, because the scheduling is done by the hardware scheduler, the processors have more time to execute application code. In addition, it will enable the configuration of massively parallel computing systems with guaranteed scheduling behavior but no additional overhead. This technology is particularly applicable in the client/server environment and transaction processing.

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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Phase II Amount
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