SBIR-STTR Award

Triply or quadruply redundant computing systems are often employed in situations where system failure would potentially cause human casualties or great financial loss. These systems utilize synchronization and voting software and/or hardware to mask the effects of a failed component in real-time. One architectural approach to implementing voting and synchronization has been to use redundant processors synchronized at the instruction (clock) level. Clock synchronous fault tolerant systems require less overhead for fault tolerance than alternative approaches. They also provide fault tolerance in a manner that can be made entirely transparent to both operating system and Applications software.However, these systems have suffered from the inability to use off-the-shelf cards or standard busses due to the design constraints needed to maintain clock synchrony. Researchers are developing a new architectural approach for insuring synchronization and determinacy that will make clock synchronous fault tolerant systems modular and capable of utilizing industry standard busses and off-the-shelf cards. These architectural innovations require experience in designing, integrating, testing, and fielding both synchronous and non-synchronous fault tolerant systems.Commercial Applications:Clock synchronous fault-tolerant systems are more efficient and easier to program than their loosely synchronized counterparts. An architectural approach and implementation that alleviates the characteristic inflexibility of this type system would be highly marketable in today's lucrative fault tolerant computing market.