SBIR-STTR Award

Intelligent I/O subsystem for CAMAC & FASTBUS
Award last edited on: 3/3/2021

Sponsored Program
SBIR
Awarding Agency
NSF
Total Award Amount
$222,256
Award Phase
2
Solicitation Topic Code
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Principal Investigator
Robert E Rajala

Company Information

Aeon Systems Inc

1704 Moon NE
Albuquerque, NM 87112
   (505) 292-1212
   N/A
   www.aeons.com
Location: Single
Congr. District: 01
County: Bernalillo

Phase I

Contract Number: 8560857
Start Date: 00/00/00    Completed: 00/00/00
Phase I year
1985
Phase I Amount
$39,256
A modular input/output subsystem is proposed to provide interface between experimental data acquisition systems using the CAMAC or FASTBUS standards and new-generation Digital Equipment Corporation minicomputers. The system offers a potential tenfold increase in the speed of data acquisition over current systems. It includes sufficient computer intelligence to manage data transfers between the experiment and computer with minimum intervention by the computer's central processor. The proposed system takes advantage of new interface bus technology to provide wide bandwidth communications and real-time data processing capability. Due to a unique relationship between proposer and DEC, the proposed system is believed to be unique. This proposal includes preliminary hardware and software design of the whole system and of one of the system modules.The potential commercial application as described by the awardee: The proposed system will find applications in high-energy physics experiments or other data acquisition systems using CAMAC, FASTBUS, or IEEE-488 data interfaces.

Phase II

Contract Number: 8619608
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
1987
Phase II Amount
$183,000
The proposal is to construct and test a prototype of a modular intelligent input/output system which is to provide the interface between data acquisition systems for large and complex experiments using the CAMAC Parallel Branch Highway and the new generation Digital Equipment Corporation (DEC) VAXBI bus. The design which has been worked out will utilize a microprocessor-based controller, the NMOS T414, which preprocesses data prior to transmission to the VAXBI bus, thus freeing the central processor of the main computer for other tasks. The subsystems speed and local intelligence will allow a greater proportion of data processing done in real time. With the real-time processing, the data acquisition system and the experiment can be timed to maximize the experimental effectiveness. The proposed system is expected to have a significant impact on the ability to collect a large amount of data at extremely high rates, which is of importance in many areas of experimental physics, but in particular in high energy physics