Time-triggered (TT) Ethernet is a standard for aerospace applications from aircrafts, hypersonic vehicles to space systems. US based technology does not currently exist. This proposal will develop IP core for use in either TT endpoint or switch. The architecture is based on LeWiz existing Ethernet MAC core and time-triggered, precision streaming technology which have been production deployed. The TT core is flexible for use in ASIC or FPGA implementation and better for commercialization purposes. The core will be synthesized for 2 US silicon fabs including a very low power and a rad-hard nodes. The design supports on or off-chip PHY with R/G/MII standards, flexible clock interface, standard AXI4 bus, highly configurable to suit low cost to high performance SOC designs. The architecture is highly scalable supporting different Ethernet speeds including Gbps. Resulting technology includes complete spec, code, verification bench, test suites, netlists
Benefit: - US based design - target US fabs - flexible application: endpoint or switch - highly configurable: suitable for low cost to low power - suitable for different technology: FPGA, 2 silicon nodes (low power, rad-hard) - Precision, low jitter design (sub uSec) - Scalable design supporting low Mbps to high Gbps speeds. - software adjustable timing - CPU offload: Low 5% CPU utilization - support priority based traffic: PCF, time-triggered, rate controlled, best effort
Keywords: Ethernet, Ethernet, aerospace standard, protocol control frame, time sensitive, best effort, rate controlled, time triggered
