SBIR-STTR Award

Research has shown that Multiple Instruction Set Architecture (Multi-ISA) computing platforms can provide significant enhancements to performance, power consumption, and security. Yet, the Commercial off-the-shelf (COTS) marketplace has not developed such a platform where differing ISA processors exist as co-processors. Popcorn Linux addresses the software needs of such a platform, but suitable COTS hardware remains absent. Such hardware should be developed to realize Multi-ISA processings demonstrated benefits . PJR Corporation proposes to develop such a processing platform where an Advanced Reduced Instruction Computer (RISC) Machine (ARM) coprocessor is built on an Enterprise and Datacenter SSD (EDSSD) 1U form factor board (SFF-TA-1007 mechanical, SFF-TA-1009 signal definition) connected to an x86_64 host via PCIe. The proposed hardware is based on the Marvell OcteonTX SoC, which is composed of Cavium ThunderX processor cores, and allows for construction of a fully functional hardware proof of concept that can be assembled from COTS components. The hardware proof of concept will be used to evaluate the software development effort required to deploy a Multi-ISA operating system to the proposed hardware, allowing commencement and evaluation of this effort prior to incurring the acquisition costs of and lead time required for the proposed hardware.

Benefit:
Popcorn Linux running on the compact, EDSFF-compliant, low-power, high-performance ARM coprocessor hardware proposed here will be immediately useful within the Navy and any other SWaP-C constrained environments. In time, it should also be able to provide increased processing density by supporting many EDSFF ARM boards in a single x86_64 host chassis. For example, a current 1U server from SuperMicro supports up to 32 EDSFF devices. Even without Popcorn Linux functionality, the proposed custom hardware could be used to immediately provide high density computation capacity using currently existing technologies. Since, the Gateworks ARM SBC will connect to an x86_64 via 10 Gigabit Ethernet, it will be possible to tie any number of them into a Software Defined Network (SDN) through their x86_64 host systems. It is straightforward to incorporate them into an elastic commuting infrastructure using Kubernetes, or similar tools, to support container-based cloud computing. Given the SWaP-C considerations being addressed by the proposed hardware, it could significantly reduce TCO of datacenter computational capacity.

Keywords:
replicated-kernel OS, replicated-kernel OS, x86_64, EDSFF-compliant, Performance, Power Consumption, arm, Energy Efficiency, Heterogeneous ISAs

Research has shown that Multiple Instruction Set Architecture (Multi-ISA) computing platforms can provide significant enhancements to performance, power consumption, and security. Yet, the Commercial off-the-shelf (COTS) marketplace has not developed such a platform where differing ISA processors exist as co-processors. Popcorn Linux addresses the software needs of such a platform, but suitable COTS hardware remains absent. Such hardware should be developed to realize Multi-ISA processings demonstrated benefits . PJR Corporation proposes to develop such a processing platform where an Advanced Reduced Instruction Computer (RISC) Machine (ARM) coprocessor is built on an Enterprise and Datacenter SSD (EDSSD) 1U form factor board (SFF-TA-1007 mechanical, SFF-TA-1009 signal definition) connected to an x86_64 host via PCIe. The proposed hardware is based on the Marvell OcteonTX SoC, which is composed of Cavium ThunderX processor cores, and allows for construction of a fully functional hardware proof of concept that can be assembled from COTS components. The hardware proof of concept will be used to evaluate the software development effort required to deploy a Multi-ISA operating system to the proposed hardware, allowing commencement and evaluation of this effort prior to incurring the acquisition costs of and lead time required for the proposed hardware.

Benefit:
Popcorn Linux running on the compact, EDSFF-compliant, low-power, high-performance ARM coprocessor hardware proposed here will be immediately useful within the Navy and any other SWaP-C constrained environments. In time, it should also be able to provide increased processing density by supporting many EDSFF ARM boards in a single x86_64 host chassis. For example, a current 1U server from SuperMicro supports up to 32 EDSFF devices. Even without Popcorn Linux functionality, the proposed custom hardware could be used to immediately provide high density computation capacity using currently existing technologies. Since, the Gateworks ARM SBC will connect to an x86_64 via 10 Gigabit Ethernet, it will be possible to tie any number of them into a Software Defined Network (SDN) through their x86_64 host systems. It is straightforward to incorporate them into an elastic commuting infrastructure using Kubernetes, or similar tools, to support container-based cloud computing. Given the SWaP-C considerations being addressed by the proposed hardware, it could significantly reduce TCO of datacenter computational capacity.

Keywords:
Heterogeneous ISAs, Performance, Power Consumption, Energy Efficiency, x86_64, replicated-kernel OS, arm, EDSFF-compliant