SBIR-STTR Award

Common Embedded Vehicle Network Diagnostics Interface Hardware
Award last edited on: 10/24/2019

Sponsored Program
SBIR
Awarding Agency
DOD : Navy
Total Award Amount
$681,944
Award Phase
2
Solicitation Topic Code
AF151-060
Principal Investigator
Richard Mourn

Company Information

FlightWire Technology Inc

1715 Smoke Ridge Drive
Colorado Springs, CO 80919
   (719) 338-7451
   N/A
   www.flightwiretech.com
Location: Single
Congr. District: 05
County: El Paso

Phase I

Contract Number: FA8650-15-M-2585
Start Date: 8/4/2015    Completed: 5/9/2016
Phase I year
2015
Phase I Amount
$149,892
The Common Embedded Vehicle Network Diagnostics Interface Hardware (CEVNDIH) program defines and implements an AS5643 optimized IEEE-1394-2008 implementation that includes changes, additions and diagnostic features. Designed with the objective of improving reliability, mission availability and improved affordability of the vehicle it is deployed in, the CEVNDIH removes unused IEEE-1394-2008 functionality, improves performance in support of AS5643 and defines diagnostic features used to improve maintenance personnel’s ability to isolate subsystem, wiring or connector faults. This Phase I proposal defines requirements and verifies the requirements are feasible. Using the requirements, a design specification is created. The design specification is then used to drive the development of the IEEE-1394-2008 optimized solution with diagnostic features. Finally, the implementation is verified to demonstrate feasibility of the implementation in preparation for integration of the PHY and Link into an FPGA in Phase II.

Benefits:
AS5643 defines a very specific use model for the IEEE-1394 bus, and, for this reason, it uses a relatively small subset of the serial bus’s capability. Optimized to support the AS5643 use case, the design provides the best possible solution, while maintaining AS5643 functional compatibility with existing chip sets. The purpose of the optimization is to remove unused requirements, which in turn translates into fewer lines of code, fewer tests, easier to achieve robustness goals, and ultimately, a more affordable solution. The addition of diagnostic features will improve the usability of IEEE-1394-2008 by helping to predictably isolate subsystem, wiring or connector faults. IEEE-1394/AS5643 is actively being investigated by the commercial aerospace industry however the lack of a DO-254 certifiable IEEE-1394/AS5643 implementation is the primary obstacle.

Keywords:
IEEE-1394b, IEEE-1394-2008, SAE AS5643, FPGA, network interface hardware, 1394 PHY Layer, 1394 Link Layer

Phase II

Contract Number: N68335-18-C-0098
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
2018
Phase II Amount
$532,052
This SBIR Phase II proposal for a Common Embedded Vehicle Network Diagnostics Interface Hardware (CEVNDIH) for an IEEE-1394 based AS5643 network implementation is focused on IEEE-1394 PHY, Link and Open Host Controller (OHCI) optimizations, diagnostics and enhancements. The resulting implementation is designed; a) to create improvements to help maintenance personnel isolate subsystem, wiring, or connector faults, b) minimize the risk of having a complete total loss of network communication by optimizing bus re-initialization process (and simplifying the overall design), c) reduce the amount of troubleshooting time by providing the information needed to detect and isolate the root cause of a vehicle communication network failure, d) improve integration (size, weight, power, and cost advantages), e) provide an affordable network upgrade path for future tactical fighter vehicle management to incorporate advanced diagnostics, protocol improvements, and speed enhancements, f) maintain open system architecture and interoperability with commercially available IEEE-1394b hardware, and g) provide ability to isolate-and-detect network failures when they occur and prevent the propagation of bus resets from occurring due to normal bus operation. The implementation shall be tested to the appropriate standard and/or specification and test for interoperability with appropriate existing IEEE-1394 chip sets.