SBIR-STTR Award

High-Speed High-Fidelity Reprogrammable Kernel for DRFM Applications
Award last edited on: 11/26/2018

Sponsored Program
SBIR
Awarding Agency
DOD : Navy
Total Award Amount
$79,949
Award Phase
1
Solicitation Topic Code
N121-034
Principal Investigator
Jeff Liu

Company Information

Euvis Inc (AKA: Euvis Corporation)

3319 Old Conejo Road
Newbury Park, CA 91320
   (805) 498-8889
   info@euvis.com
   www.euvis.com
Location: Single
Congr. District: 26
County: Ventura

Phase I

Contract Number: N68936-12-C-0178
Start Date: 6/5/2012    Completed: 12/5/2012
Phase I year
2012
Phase I Amount
$79,949
A four channel DRFM module integrated the GHz ADC and DAC with Xilinx Vertex6 FPGA on the PCB is proposed. All the components will use proven commercial off-the-self (COTS) products to minimize technical risks. The converters will be selected based on the bandwidth, broadband SFDR, latencies and synchronization capabilities. DSP core is propsoed with polyphase channelized receiver and transmitter for single signal path.The basic amplitude, phase and frequency modulations will be implemneted with frequency resolution better than 0.1 Hz. Three types of memories will be used to meet the delay and data size requirements. There will be four signal paths for a complete DRFM kernel. This DRFM module leverages the core technologies of Euvis' existing module products such as Multi-Gsps AWGs, 2 Gsps digitzers and FPGA codes. The developed DRFM will provide 500 MHz instantaeous bandwidth with 60 dB SFDR.

Keywords:
Digital Rf Memory, Digital Rf Memory, Radar, Field Programable Gate Array, Electronic Conter Measure, Digital To Ananlog Converter, Analog To Digital Converter

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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Phase II Amount
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