An FPGA-based Algorithm Accelerator for High-Performance Navy Laptop and Workstation Environments
Award last edited on: 11/1/2018

Sponsored Program
Awarding Agency
DOD : Navy
Total Award Amount
Award Phase
Solicitation Topic Code
Principal Investigator
Warren A Rosen

Company Information

Rydal Research & Development Inc (AKA: Group 16 Research and Development)

1523 Noble Road
Rydal, PA 19046
   (215) 886-5678
Location: Single
Congr. District: 04
County: Montgomery

Phase I

Contract Number: N68335-07-C-0360
Start Date: 5/9/2007    Completed: 3/31/2008
Phase I year
Phase I Amount
Rydal Research proposes to research and demonstrate the feasibility of developing an FPGA-based Algorithm Accelerator for high-performance Navy applications. The accelerator will be developed using Rydals automated algorithm-to-hardware design system. This system quickly produces VHDL designs guaranteed to be optimized in terms of characteristics such as speed, size, power, or any combination of these. The design system will be used to generate a large number of different hardware/software partitioning schemes and to perform detailed hardware designs to obtain accurate speed, size, and power predictions. The system is capable of easily translating large, complex designs and it is also able to partition the application over multiple FPGAs. The rapid design process will allow critical parts of candidate designs to be ported to an actual FPGA and demonstrated in Phase I to verify hardware simulation predictions.

The proposed approach will benefit the Navy in a number of ways. Because the process is automated, it can be used to generate a large number of designs quickly to allow for a large number of possible fine- and coarse-grain partitioning schemes to be evaluated. Since the system easily translates large, complex designs it will maximize the probability that a large part of the application will be realized in the FPGA and that substantial speedup can be achieved. In addition the system supports automated design over multiple FPGAs, which will also contribute to the likelihood that substantial speedup can be achieved. The resulting processing system will be quickly and easily upgradeable as source algorithms are improved or mission requirements change.

Time-Critical Target, Time-Critical Target, automated FPGA design environment, reconfigurable computing, rigorous image registration, optimal route planning, Field Programmable Gate Arrays

Phase II

Contract Number: ----------
Start Date: 00/00/00    Completed: 00/00/00
Phase II year
Phase II Amount