A three stage solution is proposed; 1.Preliminary Analysis, where each part has the die exposed and photographed to identify commonality at the macro level 2.Detailed Analysis,where the macro cell level schematics are developed. This stage also begins with process analysis steps with further photographs of the exposed die. Macro level (block diagram) schematics are constructed from the first pass with more detailed schematics extracted from the macro cells. Packaging options, e.g. combining functional designs on single die, are researched. 3.Design Fabrication, where the macro cells are developed. Timing and electrical models with cell data sheets are created. Once the initial environment is ready a detailed design begins. The macro cells are utilized for simulation and setup, standard cell libraries are utilized for RTL to Synthesis, Place and Route, and Static Timing Analysis. Finally the IC layout is routed followed by verification (DRC, LVS, ERC) and the output to a standard format file (GDSII). This unique method utilizes established commercial technologies and known cost saving approaches. By limiting the number of custom parts the average cost of the replacement part drops dramatically.
Keywords: Asic, Reverse Engineering, Obsolescence, Delidding, Characterization, Component Redesign, Cost Reduction, Drop-In Replacement
