A new digital signal processing architecture is proposed for electronic warfare (EW) and electronic support (ES) applications. The Reconfigurable EW/ES Processor (REW/ESP) is a flexible and expandable platform that can address a wide-range of real-time computational problems. The architecture overcomes the compute and I/O limitations of legacy systems by utilizing the latest COTS chassis with full-mesh serial backplanes, and a very large array of digital processing nodes comprised of the latest COTS 64-bit CPUs and DSP-oriented FPGAs. The Phase I effort will identify the digital signal processing algorithms that match the Navy's ES/EW program priorities and design a REW/ESP configuration on to which the selected algorithms can be efficiently and cost-effectively mapped. Under Phase II, this REW/ESP platform will be built and used for a proof-of-concept laboratory hardware demonstration of the selected EW/ES algorithms implemented on the DSP node network
Keywords:MULTI-NODE DSP LINE CARD (MDLC) FIELD PROGRAMMABLE GATE ARRAY (FPGA) ADAPTIVE BEAMFORMER ELECTRONIC SUPPORT (ES) ELECTRONIC WARFARE
