SBIR-STTR Award

There is an increasing lag between the performance gains of electronic packaging versus those of integrated circuit technology. This alarmingly widening gap poses a significant problem for high-end military and commercial electronic products. Deficiencies in packaging are actually impeding the performance of the chips. In addition to performance, lack of technology integration into packaging, such as embedded passives and thermal management, is a stumbling block for miniaturization. Area array single chip packaging is quickly becoming the de facto standard for high performance electronic products. We propose to integrate sequentially built thermoelectric cooling directly into a metal based, area array chip package followed, in a proposed Phase II, by sequentialy built thermal sensing/switching and embedded resistors. All of the electrically functional materials to be used in this effort have been developed as pastes that can be applied by inexpensive processes common to the printed wiring board and ceramic industries. All of the functional elements share common process methodology, so fabrication is streamlined and requires very little capital investment. The patterned pastes are then sintered at temperatures below 300C to achieve full functionality. Interconnect materials can be plated to achieve equivalent electrical performance to conventionally produced circuits.