SBIR-STTR Award

Power consumed in electronics is becoming a major issue for both Government and commercial systems. Commercial industry estimates that certain critical consumer electronic chips will consume 150 watts in the year 2000. Government users will find 100 watt/chip totally unacceptable for Autonomous Distributed Systems (ADS) or Spacecraft systems. The objective of both the commercial and Government designers is to greatly reduce power and to increase performance. The goal of the proposed work is to identify a path that promises to achieve ultra low power VLSI. A major ultra low power VLSI program is being undertaken by the RI (University of New Mexico) which has the promise to produce CMOS technology that operates at supply voltages near 0.25 volts. A 500 factor reduction would be realized in comparing a 5 and 0.25 process. Test circuits have been produces and a commercial foundry is becoming involved to which this technology can be transferred. The proposed STTR program will proceed in parallel with the RI program and consider ADS and commercial applications to the ultra low power research program.

Power consumed in electronics is a major issue for Government and commerical systems, and in certain distributed applications can be a determining factor when required capability, available power, operating lifetime and packaging must be balanced. Industry trends are leading semiconductor power levels lower, but not quickly enough to meet the Navy's needs, and there are indications that most commercial devices will not operate below 1 volt for the foreseeable future. These higher power levels are unaccpetable for Deployable Autonomous Distributed Sensors (DADS). The objective of this STTR project is to design, fabricate and test ULP devices for use in Navy systems. The specific devices to be built ar ea high function DSP targeted to operate at a supply voltage of approximately 0.5 volts. Picodyne will design and fabricate a ULP version of a commonly available DSP integrate it into the development environment and tool set, and package and functionally test the device. The Phase II option will result in expanded cache and on-board memory for the DSP to improve its performance in Navy applications. The devices will be fabricated in ULP on the commercial CMOS UPl foundry which is being brought on-line by the DoD/NASA funded ULP technology demonstration project.