This proposal addresses the architecture, functional top level control, system status and control, program execution control, instruction load control, data control, communications control, layered processors, pixel processors, direct execution of high level language, down loadable microcode, applicability to robotics and factory automation, implementation in vme environment, VLSI image processing, vertical communications, forth engine high level language considerations and image processing. End result would be a demonstration of a subsystem using nswc equipment, accessed via VME bus to show image processing with parallel pixel processing in a multi planar architecture. Output via IBM or NU bus will also be possible.