The complexity of VLSI circuits makes the process of developing tests a very complex and costly task. However, numerous design for testability techniques exist and are known to experts in the field. This proposal deals with aspects of the design of an expert cad system to aid a designer in creating a testable chip, and also in creating the test program itself. The work will extend research we have already carried out on this problem. The proposed system is capable of modeling existing test techniques as A.I. frames, and of automatically embedding these techniques into a chip being designed. New test techniques, as they are invented by test experts, can be easily added to the system by test experts. The proposed work deals with 4 key tasks: (1) defining a system architecture for such an expert system, (2) determining a set of bit structures and their characteristics useful for gate array circuits; (3) determining ways to calculate values for measures for test techniques so that an intelligent selection between techniques can be made; and (4) developing ways to partition a circuit so that each partition can be made testable.
