The overall goal of the proposed Phase I SBIR project is to develop and demonstrate 256x256 segmented readout integrated circuits (ROICs) that can read, digitize and count the response of linear-mode single photon counting avalanche photodiode (APD) pixels with picosecond readout capability and bandwidth at least an order of magnitude better than currently available ROICs. We will accomplish this by designing an ultrahigh speed front-end amplifier for an existing ROIC architecture that will be capable of low noise, wideband amplification of picosecond photocurrent pulses induced by single photons in the APD. In Phase I of this project, we will design, model and simulate the performance of higher speed ROIC analog front ends that will enable readout speed enhancement by as much as a factor of 10 compared to the performance of existing ROICs. In Phase II, we will design, fabricate and test 256 x 256 ultra-high speed ROICs and 256 x 256 linear-mode APD arrays.
