SBIR-STTR Award

This research will ultimately produce an interactive algorithm design tool for embedded multiprocessor systems. Designers will specify algorithm structure as a directed graph of interconnected nodes. The tool automatically partitions these graphs into tasks and then assigns these tasks to processors. These groupings and assignments will optimize algorithm performance (i.e., throughput and processing delays) based on the target multiprocessor system's characteristics: distributed operating system, network topology and hardware. The optimized tasks will be translated into an ada template to support algorithm implementation on a target multiprocessor system. The innovation in this research is the unique combination and integration of graphics, optimization, algorithm evaluation, and code generation technologies which effectively decouple algorithm functionality and computational complexity issues from implementation level performance decisions. By automating much of the design process, producing optimal graphs, and ensuring that the code is traceable to the design, the software development process will be less costly, more timely, and more reliable. Three technical objectives will demonstrate the technical feasibility of the interactive algorithm design tool: (1) develop a graphical algorithm specification language, (2) devise a technique to generate target optimal implementations of parallel algorithms, and (3) design an automatic technique to translate optimized graphs into ada code templates.