Based on a new construct, this approach employs repeated application of an existing block cipher in a random sequence to significantly decrease the SNR available to power line attacks and increase the number of recorded events necessary to conduct DPA attacks. The objective is to demonstrate the feasibility of a randomized block cipher architecture and it's ability to reduce side-channel information leakage in FPGA designs.
Keywords: Fpga, Randomized Block Cipher, Dpa Resistant, Aes, Side-Channel Leakage, Power Line Attack
