SBIR-STTR Award

Traditional RADAR implementations suffer from bulky transmitters with cluttered microwave plumbing and antenna support systems that make systems expensive. Today, phased array transceiver architectures providing moderate power (10–100W) can provide RADAR performance with beam-steering capabilities with modest size of the systems. However, these conventional phase array architectures do not scale well to compact, low cost RADAR applications as the III-V semiconductor technologies are mainly used for the RF circuitry while silicon digital CMOS technology is employed for control and timing circuits. Thus, making the assembly, packing and characterization processes high cost and low yield. To achieve truly low cost and compact size, it is necessary to integrate as much of the active circuitry as possible into single chips – as in the handset industry. Here, we proposed a new T/R IC architecture that will include on-chip digital control compensation networks to ensure performance uniformity at the element level. We aim to achieve all functionalities necessary to make a robust scalable TRIC system with the addition of RF build-in-self-test (RF-BiST) capability to reduce cost and increase system robustness. We will show that our proposed system architecture and components can provide a low-cost, high-performance single-chip TRIC for scalable phase-array X-band RADAR solution.

Keywords:
X-Band Radar, Phase Array, Beamsteering, Coupled Vco Array, Non-Linear Coupled Networks, Bist, Self-Calibration