We have developed engineered epitaxial layers based on nanostructure technology that can be applied in hardening a wide variety of integrated circuits processes against total dose degradation, single event upsets (SEU) and single event transients (SETs) by minimizing collected photocurrents (electron-hole pairs) via recombination centers. These nanostructure-engineered substrates could provide an ideal solution across a broad range of process nodes. We will first focus our attention on processes involving LOCal Oxidation of Silicon (LOCOS) since most ICs that are used in Ballistic Missile Defense Systems (BMDS) utilize LOCOS processes. After that we would widen the processes to include other processes. Radiation Assured Devices in conjunction with Ball Aerospace is currently running a test lot of engineered substrates with TI. Under this proposed Phase I effort we would characterize the test chips obtained from the current TI run (due for delivery in January 2009) for radiation hardness, electrical performance (power, speed leakage, etc) and long term reliability and prepare a Phase I final report in conjunction with Texas Instruments on migrating the engineered substrate technique to other technology nodes.
Keywords: Nanotechnology, Locos, Radiation Hardness, Epitaxial Layers, See, Seu, Set, Total Ionizing Dose
