SBIR-STTR Award

Eutecus proposes to develop scalable focal-plane sensor-processor array chips, equipped with InGaAs sensor sensitive in the near infrared range. As opposed to the traditional integrating type approach, the sensor interface in our proposed design will contain precise transimpedance amplifiers and 8-12 bit AD converters, which allow significantly higher sampling rate. In this way, the incoming image frequency will go up to the few hundred kilohertz (kHz) or even to a few megahertz (MHz) region, which is critical in case of Fourier analysis of the incoming pixel information. The sensor array will be mapped into a high performance processor array. Each of the processors of the array will handle one or a few pixels. The processors will be equipped with minimum 128 bytes of memory per pixel, a multiple-add type arithmetic unit, a special statistical unit, and a morphology unit. In this way, the proposed sensor-processor chip will be able to perform Fourier analysis or calculate other kinds of computationally heavy linear (e.g. mean, convolution) or non-linear (e.g. min, max, median) or binary (mathematical morphology) filters, and provide the processed output with a few thousand frames per second speed. The output can be either an image or a decision or both, which can alarm the main processor of the host system when a certain target or special visual event occurs.

Keywords:
• Near-Pixel Processing, • Non-Integrating Type Sensor, • Focal Plane Processor Array,

Eutecus proposes to develop scalable focal-plane sensor-processor array chips, 3D integrated with various sensors (e.g. InGaAs) sensitive in different IR spectral domains (e.g. NIR-SWIR). As opposed to the integrating type approaches, the sensor interface (read-out integrated circuit, ROIC) of the proposed design will contain precise resistive trans-impedance amplifiers (RTIAs) and fast analog-to-digital (AD) converters tightly coupled to a digital processor array, which will allow very high temporal sampling rates combined with near sensor algorithmic calculations. The proposed device will be able to handle input frequencies up to the megahertz (MHz) range. The processors will be equipped with local data memory per pixel, a multiple-add type arithmetic unit, a special statistical unit, and a morphological unit. The proposed sensor-processor chip will be able to perform Fourier analysis or calculate other computationally intensive linear (e.g. mean, convolution), non-linear (e.g. min, max, median) or binary (mathematical morphology) operations, and provide the processed output at a speed of few thousand frames per second. The output can be either an image and/or a decision, being able to trigger instantaneously the main processor of the host system when a certain object / target or a special visual event (identified through its space-time-spectral signature) occurs.

Keywords:
Key Words: • Near-Pixel Signal Processing, • Non-Integrating Type Sensor, • Focal Plane Sensor-Processor Array, • Read Out Integrated Circuit (Roic), ---------- The main goal of the proposed program is to develop and integrate a laser ranger processor/engine based on Eutecus'XENON line of massively parallel, cellular many-core processors (TRL 5) with a recently prototyped multi-channel fusion-tracking processor/engine (TRL 6). The implementation will be completed in defense-grade rad-tolerant/rad-hard field programmable gate array (FPGA) technology also improving the robustness of space-time and spectral domain signature analysis and tracking performance. Eutecus will work closely with leading FPGA Vendors (Xilinx, Inc., Altera Co.) and several Defense Prime Contractors (LMSSC, Raytheon and Northrop) to meet MDA requirements for several key program elements (primarily ABMD and ABIR) of the Ballistic Missile Defense System (BMDS). Eutecus proposes to design and develop the next generation of two key elements of future interceptor seekers: (i) a range imager front-end sensitive in the 800-1400 nanometer wavelength (NIR/SWIR) operating at frame rates above 10kHz; and (ii) a three-channel, scalable multi-core processor back-end with embedded fusion-tracking algorithms supporting real-time multi-spectral (SWIR-MWIR-LWIR) feature/signature analysis and calculations required for range imaging and fusion-tracking at ultra-high speeds (typically in the 1-10 kHz range). Prototype hardware will be developed in Phase II combined with field tests in order to validate the technology for Phase III transition.