We propose to investigate, design and prototype capabilities of a visual and friendly workbench environment called TimeBench for designing, modeling, analyzing, reusing and integrating object-oriented real-time systems. Class hierarchies and timing information of real-time and embedded systems will be represented visually and consistently. Object hierarchies and specified timing constraints will be used to generate code for specific targets and programming languages. Subsystems can be coded incrementally while retaining the timing behavior of the final workload. Any custom code added will be parsed to re-generate visual and semantic information automatically. A catalogue facility will enable COTS and custom components/classes to be reused consistently. Class hierarchies will be represented using real-time extensions to UML (Unified Modeling Language) resulting in RT-UML, which captures timing, scheduling and concurrency information in addition to relationships between subsystems, modules and classes. RT-UML representation will be tightly integrated with the timing analysis capabilities of TimeWiz, a tool which applies rate-monotonic analysis techniques. TimeBench will support a very large number of components and also be open and extensible, allowing software modules with new analysis techniques to be added as plug-and-play units.
Keywords: Hierarchical Visual Design, Component Catalog object-Oriented Programming, Real-Time Umltiming & Reli
