CR proposes a prog am of research to develop a new technique for suppressing single event latchup (SEL) in ICs that would be adequately radiation tolerant, except for their susceptibility to single event induced latchup. SEL suppression has, up till now, required the use of wafer preparation technologies such as SOI, SOS, etc., which are not used by mainstream IC manufacturers. The technique proposed herein would greatly enhance the ability to upgrade COTS ICs to rad-tolerant (Rt) chips through non-intrusive modifcations to commercial fabrication processess. Using this technique, space systems manufacturers could procure a much wider range of part types from a wider range of suppliers, and by conducting some additional post-manufacturing operations, make them immune to SEL.
Keywords: Single Event Latchup (Sel) Technique For Rad-Tolerant Ics Sel Suppression In Ics Non-Intrusive Hard
