SBIR-STTR Award

DTRA uses High Fidelity Computer Codes (HFCC) to investigate weapon effects and techniques for countering Weapons of Mass Destruction (WMD). End-to-end HFCC simulations in support of the DTRA Agent Defeat Warfighter Capability will require calculations including multiple phenomena that occur in vastly different time scales (-sec to hours). As DTRA becomes increasingly reliant on computational modeling and simulation for these security-critical tasks, efficient use of existing computational resources and planning and optimizing for next generation architectures becomes paramount. HFCCs typically are memory-bound codes and much CPU time is wasted waiting for the data needed to perform a computation. Emerging innovations in memory technology that mitigate memory performance issues, therefore, come at a critical time and optimizing HFCCs for pre-exascale systems that feature such technologies must start now. To enable such optimizations, this project proposes to build the MemInsight tool for analyzing application memory address streams of HFCCs to identify access patterns, the extent to which different levels of memory are exploited, memory footprint, and key data structures. The resultant data forms the basis for issuing guidance for HFCC refactoring and optimization.

DTRA uses High Fidelity Computer Codes (HFCC) to investigate weapon effects and techniques for countering Weapons of Mass Destruction (WMD). End-to-end HFCC simulations in support of the DTRA Agent Defeat Warfighter Capability will require calculations including multiple phenomena that occur in vastly different time scales (µ-sec to hours). As DTRA becomes increasingly reliant on computational modeling and simulation for these security-critical tasks, efficient use of existing computational resources and planning and optimizing for current and next-generation architectures becomes paramount. Current and upcoming supercomputing platforms feature many-core processor designs with elaborate memory hierarchies. In order to get the best performance out of these machines, DTRA’s application scientists and HFCC developers will need easy-to-use performance profiling tools to discover bottlenecks in their code. To that end, EP Analytics is developing the MemInsight tool-suite that can simultaneously analyze both memory usage and thread-level parallelism to provide intuitive and actionable performance optimization insights to code developers.