The objectives of this task are to: 1. Characterization of both ionizing and displacement damage radiation effects in Metal Oxide Semiconductor (MOS) ultra-deep submicron (< 90nm) integrated circuits and compound semiconductor technologies and also to 2. Development and demonstration of minimally invasive methods to mitigate these radiation effects in ultra-deep submicron digital and analog/mixed-signal integrated circuits. The successful outcome of this task will support the use of ultra-deep submicron integrated circuits in DoD satellite systems that will result in very significant savings in weight, power and reliability for systems that include Space Radar, Space Tracking and Surveillance Systems, TSAT and others. Each new generation of microelectronics results in performance benefits that include > 2X in integration density, > 4X in power savings and > 2X in operating speed making possible very significant improvements in system capabilities. In addition, this task will also support the use of compound semiconductor technologies (e.g. Antimony Based Compound Semiconductors, Indium Phosphide, and others) in these systems and their introduction into advanced spacecraft and missile systems with similar savings in both power and weight and coupled with increased performance. DESCRIPTION: Currently satellite systems are fabricated using a mix of commercial and radiation hardened circuits. However, the use of advanced commercial integrated circuits devices results in added complexity to mitigate radiation effects that can result in the mal-operation and/or destruction of devices. In many cases, the penalties in increased power, area, weight and added circuit complexity out-weigh any potential benefits and preclude the use of the advanced commercial technology. In addition, there has been an increase in the introduction of compound semiconductor technologies in these systems for specific high performance applications. Moreover, these technologies have demonstrated a sensitivity to radiation effects. The present methods to mitigate radiation effects while proven to be effective at circuits geometries > 150nm have been shown to be less effective when applied to integrated circuit feature sizes below 100nm and many of these compound semiconductor technologies. Thus, if minimally invasive methods such as the use of alternative materials, circuit enhancements, and other innovative approaches could be developed to reduce radiation effects sensitivity these devices could be used with little or no penalties. Therefore, the basic approach to accomplish this task would be to leverage commercial microelectronics at the < 90nm nodes and augment these technologies with radiation mitigation techniques that would have minimal impact on the electrical performance and manufacturability. This same approach also applies to the radiation hardening of the compound semiconductor technologies. Additionally, the development of such methods requires the development of cost effective methods to model and simulate the radiation response of these < 90nm and compound semiconductor technologies. Without a robust modeling and simulation capability it would be both technically and economically unfeasible to develop these mitigation methods. PHASE I: Identification of minimally invasive methods, including material approaches, to mitigate radiation effects in < 90nm microelectronics technologies including III-V and SiGe materials systems. Development of cost effective radiation effects modeling and simulation methods for < 90nm microelectronics and compound semiconductor digital and analog/mixed-signal microelectronics. PHASE II: Electronic Design Automation tools (programs) that can; o Identify design sensitivities in complex integrated circuits o Design radiation insensitive integrated circuits o Perform trade studies to provide optimized integrated circuits WRT radiation and electrical performance o Analysis the radiation response of complex integrated circuits Technology Computer Aided Design (TCAD) tools that can: o Provide cost effective 3-D models to support the simulation of the radiation response of nanotechnology microelectronics. o Identify radiation sensitivities at the transistor level Mixed-Mode and Level Simulation systems that can effectively couple the radiation response at the transistor level to higher levels of circuit and subsystem integration (e.g. transistor response to small circuit to complex circuit to sub-system ) to support the accurate radiation response simulation up to and including the sub-system level. Radiation effects Product Design Kits (PDK) that combine the electrical and radiation response design and modeling parameters for a specific technology. PDKs are provided by semiconductor manufacturers to their customers to support design activities. In general a semiconductor manufacturer will develop an electrical performance and design PDK that must be then augmented with radiation performance to support customer s that require the technology to be used in a radiation environment. Development and demonstration of < 90nm radiation effects modeling and simulation methods PHASE III DUAL USE APPLICATIONS: Use of the mitigation, modeling and simulation methods developed through this effort to support the use of advanced microelectronics for terrestrial application such a very high performance microprocessor, advanced Servers, and very large cache memories. REFERENCES: 1. IEEE Transactions on Nuclear Science; December 2005, Volume 52, Number 6, Session A Single Even Effects: Mechanisms and Modeling, pages 2104-2231 2. IEEE Transactions on Nuclear Science; December 2005, Volume 52, Number 6, Session F Single Even Effects: Devices and Integrated Circuits, pages 2421-2495 3. JEDEC 57, SEE Test and Characterization Guidelines and Test Method 4. Military Test Method 1019, Steady State Total Ionizing Dose 5. ASTM 1892 Steady State Total Ionizing Effects Guideline
Keywords: Single-Event Effects, Single-Event Upset, Single-Event Transients, Total Ionizing Dose, Displacement Damage
