Full Circle Research proposes a Phase II SBIR program to continue the development of a new technique for suppressing single event latchup (SEL) in COTS ICs. SEL suppression requires the use of wafer preparation technologies such as SOI, SOS, etc., of fabrication of ICs in an epitaxial layer of silicon on a wafer of heavily doped silicon. The latter is already widely used in commercial IC manufacture, and is much preferred over the former. For epitaxial processing to work, however, the layer must be thin, e.g. less than 6mm1 thick in today's technologies and thinner still in future technologies. Often this is not the case. FCR's technique involves implanting a heavy ion from the back of the to within a few microns of the top surface. Back-surface implantation could occur at the wafer level, or after the chip is packaged, and thus would be non-intrusive, and would greatly facilitate upgrading COTS ICs to rad-tolerant (RT) chips. Using this technique, space system manufacturers could procure a wider range of part types from a wider range of suppliers, and make them immune to SEL. Space system manufacturers must be able to procure ICs that function in a space radiation environment. Non-intrusive process changes have already been identified that permit many ICs to satisfy space mission requirements for ionizing dose, but single event latchup continues to be a major limiter in attempts to use advanced ICs in space. An affordable method of suppressing SEL in ICs fabricated in commercial processes would dramatically advance the technology for producing radiation tolerant ICs, and permit the use of advanced COTS ICs in commercial and military systems concerned about SEL.
Keywords: Single Event Latchup (Sel) Technique For Rad-Tolerant Ics, Non-Intrusive Hardening Techniques, Sel S
