Several projects in High Energy Physics that are under construction involve specialized highly accurate timing devices using LGAD detectors [1]. The immediate projects are aimed at the High Luminosity upgrade of the LHC (HL-LHC) with separate upgrades planned for both the ATLAS [2] and CMS [3] detectors. The expected timing resolution per measurement is expected to be ~30 picoseconds with a spatial granularity of 1.3mmx1.3mm. The LGADs planned do not allow significantly improved granularity but a recently introduced version (AC-LGAD, while previous devices are DC coupled) should allow truly 4-dimensional tracking with good spatial and timing resolution. In addition, by thinning the detector one can anticipate the possibility of 10 picosecond timing resolution per measurement [4]. For these newer AC-LGADs there is a complete lack of readout electronics using VLSI chips. There are many challenges to the development of readout electronics that go well beyond the electronics developed for the HL-LHC. These include the need for high density and low power necessitated by the use of smaller pixels and improved timing precision to allow 10 picosecond timing measurement. The use of charge sharing can be used to avoid too small a pixel size but this puts a premium on achieving low noise in the electronics front-end. Here we propose a custom integrated circuit optimized for timing resolution, while keeping the other design specifications well inside tolerable levels for HEP particle detection applications. The circuit topology will be similar to previous proven fed back common emitter amplifiers, using a TowerJazz SBC35MTK SiGe BJT process with >10 Ghz ft transistors. The SBC35MTK process also features very good resistor matching, high early voltage, good transistor, all of which support good channel yield, low channel variation and ease of design for signal processing after the front end amplifier. Additionally, the lower base resistance of SiGe transistors allow for better noise vs power consumption performance when compared to other Si transistor technologies. The proposed design will have a low noise preamp, possibly a second gain stage with buffered analog output intended for pico-probe measurements, and a comparator with digital output. The buffered output will assist in the characterization of the readout chip and possible detector candidates. Our plan is an initial 16 channel chip in order to give more confidence in successive design iterations as well as comparison to our simulated performance on the AC-LGAD. Initial simulation results are very promising. See figure 1 for pre irradiation jitter vs power consumption for several input transistor sizes and total input capacitances. The simulated input signal was a 150 ps risetime, 250 ps fall time current pulse with a total integrated charge of 4 fC, which is similar to the input we expect [5]. The jitter of the readout system could be improved slightly in theory with a higher ft process. But, generally, faster transistors will take even more power and the achievable total system jitter is limited to around 10 ps by Landau fluctuations in the detector itself. The proposed IC would position Anadyne, SCIPP, and collaborators to do important follow up work: bonding the IC to a detector for detector characterization, irradiating the ICâs to characterize rad hardness, and doing some large sample size statistics to determine good channel yield
