SBIR-STTR Award

A New Cost-Effective Engineered Substrate
Award last edited on: 1/23/20

Sponsored Program
SBIR
Awarding Agency
DOE
Total Award Amount
$199,031
Award Phase
1
Solicitation Topic Code
30b
Principal Investigator
Robert Patti

Company Information

Nhanced Semiconductors Inc

1415 Bond Street Suite155
Naperville, IL 60563
   (331) 701-7070
   N/A
   www.nhanced-semi.com.com
Location: Single
Congr. District: 06
County: DuPage

Phase I

Contract Number: DE-SC0019859
Start Date: 7/1/19    Completed: 3/31/20
Phase I year
2019
Phase I Amount
$199,031
Silicon-based sensors are central to particle physics experiments and particle tracking detectors. Users now demand smaller mass, higher data rate, smaller pixels, and sophisticated front-end processing. Lowering the system mass mitigates loss of information due to multiple scattering and conversions as particles traverse a vertex plane. However, the ionization signal is generally proportional to the sensor thickness. Thus, both radiation damage and the use of thinner sensors result in smaller ionization signals seen by the electronics. It is critical to develop internal amplification structures within a sensor to solve the signal to noise problem. Although LGAD (Low Gain Avalanche Diode) devices have very promising gain features, their exposure to radiation translates to increased current leakage and gain loss. Such sensitivity makes LGAD unsuitable for HEP in its current state. NHanced and SLAC National Accelerator Lab propose to develop a new process technology to fabricate LGAD devices on an engineered substrate. The substrate will have an extra-steep N+/P+ junction doping profile. This would give higher initial gain and extra margin for acceptor loss due to radiation damage. Unfortunately, no existing process technology allows implantation of a steep, sharp profile at the depth required by our application. However, we believe this could be achieved by engineering a new substrate by (1) fabricating the N+ layer on one wafer and the two P+ layers on another wafer and (2) bonding them together using a low temperature silicon-silicon bonding technology. Such technology will enable the fabrication of a new class of radiation hardened LGAD devices. In Phase I we will leverage SLAC low temperature microwave annealing technology (MWA) to develop a low-temperature, low-cost manufacturable Si-Si bonding process. We believe this technology will provide enough kinetic energy to the silicon dislocations to recrystallize the lattice at the bonding interface. We intend to develop the bonding technology through multiple blank wafer bonding trials. We will target a Si-Si bonding energy greater than 1.5J/m2. We will demonstrate our technology by (1) fabricating a P-I-N diode pixel arrays sensor prototype on and engineered wafer, (2) bump-bonding the prototype to an existing ePix ROIC, and (3) performing functional radiation testing to validate performance.The anticipated low-temperature Si-Si bonding technology will be relevant to HEP/LEP for particle trackers, particle physics experiments, and commercial applications such as digital X-rays and PET scanners. It is also a completely new paradigm for building 3D heterogeneous monolithic wafers, enabling new applications because of lower cost, easier manufacturing, and potentially new hybridized 3D devices.

Phase II

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Start Date: 00/00/00    Completed: 00/00/00
Phase II year
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