SBIR-STTR Award

Extremely good timing resolution is becoming more and more important in both high energy collider detectors and for commercial industry applications such as LIDAR for self-driving cars. The needs have grown such that resolutions at the 1 ps level are desired, since better resolutions leads to better performance. Unfortunately, the electronics capable of 1 ps resolution, and the ability to send a synchronous clock with sub-5 ps jitter to timing electronics separated by 10-20 meters, does not currently exist. We are designing a board based on the DRS4 ASIC, which does have 1 ps resolution but which does not work for many applications, particularly for collider detectors, because of the short 205 ns buffer when operated in the normal design. We implement a locally triggered, region-of-interest readout that digitizes just the regions where there is a signal above threshold, and can thus store the signal in a digital buffer for later retrieval, thus extending the effective buffer depth tremendously. We will use commercially available jitter reducing PLLs from Silicon Labs and other vendors, which are rated for 90 fs phase jitter, to test whether a sub-5 ps jitter synchronous fanout can be developed using off-the-shelf components. We will develop a DRS4FEM analog board consisting of the DRS4 ASIC, 8-ch 40 MHz ADC, and fast comparators for a signal timestamp to test our concept for building a 1 ps capable, deeply buffered, board around the DRS4. We also will build a clock fan-out using PLLs from Silicon Labs and other vendors, which will let us test whether a sub-5 ps jitter synchronous clock can be propagated to electronics separated by 10-20 meters. Our board would effectively be a very affordable oscilloscope (an order of magnitude cheaper than comparable oscilloscopes). The lowered cost of our scope will greatly expand the number of research groups that can afford to do research in fast time. We should also benefit the LIDAR community.