SBIR-STTR Award

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. To address this issue, we assembled a consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high performance memory controller IP development – to collaboratively develop a commercialization path for a photonic Memory Controller Module (P-MCM), targeted to meet the following specifications: (1) Provide optical interconnects between sever-class multiprocessor chip and multiple (> 10) high density stacked memory modules; (2) Target at the next-generation high density stacked memory modules, including High Bandwidth memory (HBM), Hybrid Memory Cube (HMC), and Wide I/O, etc; (3) Power efficiency – not larger than 0.5 pJ/bit; (4) I/O bandwidth – 5 TB/s aggregate I/O rate for each memory module; (5) Network reconfigurability at nanosecond scale– optical switching fabric and fast tunable laser; and (6) Wavelength division multiplexing (WDM) and optical multicast. During Phase I: (1) Columbia University will coordinate the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia will develop high performance memory controller IPs and interfaces in FPGAs platform; (2) Freedom Photonics will develop the programmable, tunable laser using mature InP/GaAs processing; (3) Analog Photonics will develop the photonic transceiver and interconnect fabrics using silicon photonic processing through the American Institute for Manufacturing (AIM) Integrated Photonics multi-project wafer and assembly (MPWA) facilities; (4) PLC Connections will package the photonic transceiver and interconnect fabric chips and tunable laser chips, and provide a low-loss and robust optical coupling mechanism; and (5) Antario will assemble the packaged chips with other components (e.g. FPGA, RF amplifiers) on to a custom designed PCB.

As computational density for high-performance computing and big-data services continues to scale, performance scalability of next generation computing systems is becoming increasingly constrained by limitations in memory access, power dissipation and chip packaging. The processor-memory communication bottleneck, a major challenge in current multicore processors due to limited pin-out and power budget, presents a detrimental scaling barrier to data-intensive computing. General statement of how this problem is being addressed: A consortium team of small businesses and leading researchers that includes experts from photonics processor-memory architecture, III/V photonic laser design/fabrication, silicon photonics design/fabrication, photonics packaging and assembly, and FPGA-based high performance memory controller IP development – to collaboratively develop a commercialization path for a Photonic Memory Controller Module (P-MCM). What was done in Phase I: Columbia University coordinated the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia developed high performance memory controller IPs and interfaces in FPGAs platform. Freedom Photonics developed the programmable, tunable laser using mature InP/GaAs processing. Analog Photonics developed the photonic transceiver and interconnect fabrics using silicon photonic processing. PLC Connections packaged the photonic transceiver and interconnect fabric chips and tunable laser chips and provide a low-loss and robust optical coupling mechanism. What is planned for the Phase II project: Columbia University will continue to coordinate the working group and subgroups to provide the system architecture and specifications for each small business consortium team members. Columbia will update high performance memory controller IPs and interfaces in FPGAs platform to meet Phase II goals and perform a final end-of-Phase II P-MCM demonstration. Freedom Photonics will develop and package a 17-channel integrated source laser array. Analog Photonics will design, fabricate and package switch, photonic transceiver, driver IC and interconnect fabrics using silicon photonic processing. PLC Connections will develop high density, low cost I/O packaging technology to interconnect the ICs and components developed in this program using dense fiber arrays to provide a low-loss and robust optical coupling mechanism, and deliver packaged prototypes to Columbia for system integration and demonstration. Commercial Applications and Other

Benefits:
The Photonic Memory Controller developed have wide commercial applications in data center and telecom markets.