The data acquired from high-bandwidth high-resolution detectors, such as in Elementary Particle Physics experiments, often requires significant digital signal processing before it is used in triggering or pattern recognition algorithms. This processing, although not extremely complicated algorithmically, can utilize massive amounts of processing power, and is best performed as soon as possible after the data are processed by the digitization electronics, in order to minimize latency and possibly reduce downstream bandwidth requirements. If possible, configurable (but not software-programmable) hardware to accomplish this purpose should be embedded in the interface between the digitization electronics and standardized networks. In this project, a hardware vector processing capability will be added to a high-bandwidth architecture for interfacing between point-to-point fiber-optic links that carry data from detector electronics. The architecture is based on field-programmable gate array (FPGA) technology with embedded power processors. The added capability utilizes digital signal processing elements within the FPGA to process in-memory data structures after the data in those structures are received from the front ends and prior to shipping the structure contents to a commodity network.
Commercial Applications and Other Benefits as described by the awardee: The technology should be employed in network data acquisition interface cards for Elementary Particle Physics experiments. Other applications include detectors for Particle Astrophysics, such as the camera for the proposed Large Synaptic Survey Telescope. The use of such techniques would lead to less costly data processing centers downstream of the data acquisition, as well as more timely availability of highly processed data
